1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to an on die termination apparatus and a method of controlling the same.
2. Related Art
In general, when a signal transmitted through a bus line having a predetermined impedance meets another bus line having a different impedance, a part of the signal is lost. A technique for reducing the loss of signal by matching the impedances of the two bus lines is referred to as on-die termination (hereinafter, referred to as ODT).
As illustrated in FIG. 1, a general ODT apparatus includes a first D/A converting unit 10, a first comparing unit 20, a first counter 30, a second D/A converting unit 40, a second comparing unit 50, a second counter 60, and a pulse generating unit 70.
The first D/A converting unit 10 outputs a first voltage ZQP corresponding to a first code PCODE<0:4> according to a first pulse ENABLE. The first comparing unit 20 compares the first voltage ZQP with a reference voltage VREF according to the first pulse ENABLE and a second pulse CPOUTP and outputs the result signal COMP_OUTP. The first counter 30 counts up or down the first code PCODE<0:4> according to a third pulse PCOUNT to correspond to the result signal COMP_OUTP. The second D/A converting unit 40 outputs a second voltage ZQN corresponding to a second code NCODE<0:4> according to the first pulse ENABLE. The second comparing unit 50 compares the second voltage ZQN with the reference voltage VREF according to a fourth pulse CPOUTN and the first pulse ENABLE and outputs the result signal COMP_OUTN. The second counter 60 counts up or down the second code NCODE<0:4> according to a fifth pulse NCOUNT to correspond to the result signal COMP_OUTN. The pulse generating unit 70 generates the first to fifth pulses.
As illustrated in FIG. 2, the first comparing unit 20 includes a primary comparator 21, a transistor M13, a secondary comparator 22, a driver 23. The primary comparator 21 that compares the first voltage ZQP to the reference voltage VREF according to the first pulse ENABLE and outputs the result signals V1 and V1B. The transistor M13 makes the result signals V1 and V1B have the same level according to the first pulse ENABLE. The secondary comparator 22 compares the result signal V1 to the result signal V1B according to the second pulse CPOUTP and outputs the result signals V2 and V2B. The a driver 23 drives the result signals V2 and V2B and outputs the result signal COMP_OUTP. The secondary comparator 50 has the same structure as the primary comparator 20.
The operation of the ODT apparatus for a semiconductor memory having the above-mentioned structure according to the related art will now be described with reference to FIG. 3.
At a timing A1 when the first pulse ENABLE changes to a high level, the first D/A converting unit 10 starts to operate and outputs the first voltage ZQP. Also, at the timing A1, the primary comparator 21 of the first comparing unit 20 compares the first voltage ZQP with reference voltage VREF and outputs the signals V1 and V1B.
At a timing A2 when the second pulse CPOUTP changes to a high level, the secondary comparator 22 of the first comparing unit 20 compares the result signal V1 to the result signal V1B and outputs the result signals V2 and V2B to the driver 23, and the driver 23 drives the result signals V2 and V2B to output the result signal COMP_OUTP.
Then, at a timing A3 when the third pulse PCOUNT changes to a high level, the first counter 30 counts up or down the first code PCODE<0:4> according to the result signal COMP_OUTP and outputs the count result to the first D/A converting unit 10, thereby adjusting the first code PCODE<0:4>.
The second D/A converting unit 40, the second comparing unit 50, and the second counter 60 operate according to the first pulse ENABLE, the fourth pulse CPOUTN, and the fifth pulse NCOUNT in the same manner as the first D/A converting unit 10, the first comparing unit 20, and the first counter 30, thereby adjusting the second code NCODE<0:4>.
A cycle in which the first code PCODE<0:4> and the second code NCODE<0:4> have been adjusted is repeated a predetermined number of times, thereby completing an ODT operation.
However, the ODT apparatus for a semiconductor memory according to the related art has the following problems.
According to the ODT apparatus, the voltages are generated according to the codes while at the same time the comparing operations start. However, at the timing when the comparing operations start, voltage levels according to the codes do not have exact logic values. For this reason, errors occur in the comparison results and thus the ODT is not exactly performed.
Further, when a low voltage VDD is applied to the semiconductor memory, regardless of the comparison timings, the levels of the result signals output from the first comparing unit are too low to normally perform the comparison operation of the second comparing unit. As a result, errors occur in the comparison results and thus the ODT is not exactly performed.